1. Field of the Invention
The present invention relates to semiconductor integrated circuit memories, and more particularly, to a circuit for providing redundant columns in such memories when other portions of the memory are found defective.
2. Description of the Prior Art
In integrated circuit memories, a single defect in any portion of the array of memory cells may render the entire memory useless. Furthermore, as improvements in the design and fabrication of integrated circuits are made, greater numbers of memory cells are being placed on a single chip and as a result, very large scale integrated circuits are made. In such case, the probability of producing one or more defective memory cells will be easily increased and the entire memory will be rendered useless.
As prior art to solve such a problem, integrated circuit memories have been designed and fabricated in such a manner that spare memory cells in addition to normal memory cells are arranged on the same chip in order to substitute defect-free spare memory cells for defective normal memory cells. To achieve such substitution, integrated circuit memories need decoder circuits: normal decoders which may be used to disable address signals selecting a row or a column associated with defective memory cells and spare decoders which may address a row or a column associated with defect-free spare memory cells with said address signals.
After the fabrication of the integrated circuit memory, it would be tested to determine whether memory cells had been defective, or not. If rows or columns including normal memory cells are determined to be defective, integrated circuit memories will be programmed in such a manner that a spare decoder including defect-free spare memory cells may be enabled by address signals selecting the defective normal memory cells and then, a normal decoder selecting a row or a column corresponding to defective normal memory cells may be disabled by said address signals.
There are two ways of programming in that manner: one way by using nonvolatile memory elements and the other way by blowing polysilicon fuses. Again, the way of blowing the fuses can be divided into the use of laser spots and that of electrical current.
Currently, according to the development of the semiconductor device manufacturing process, there has been a redundancy scheme in which blocks including defective normal memory cells may be replaced with spare blocks including defect-free spare memory cells. For example, assuming that 64K normal memory cells are divided into 4 blocks of 16K memory cells, fault of one cell of 16K memory cells constituting each block requires the replacement of the defective block with a defect-free 16-K spare memory cell block.
In a dynamic random access memory, the row redundancy of substituting the faulty normal row line for the defect-free spare row line can be easily accomplished without more difficulty. However, the column redundancy raises some problems. When the spare decoder disclosed in the U.S. Pat. No. 4,228,528 is used in a semiconductor dynamic random access memory device, such device needs to include circuits for detecting the column address transition in a static column mode operation. As a result, such on-chip addition of column address transition detection circuits incurs the drawback of increased chip size.
For example, FIG. 1 and FIG. 2 are circuit diagrams illustrative of the normal decoder and spare decoder respectively as prior art circuit diagrams performing the column redundancy with laser fusing.
A column line (or bit line) of the normal memory cell array is connected to a line 8 of FIG. 1. A column line of the spare memory cell array is connected to a line 18 of FIG. 2.
Therefore, in case of substituting the column line of the normal memory cell array, the operation of the column normal decoder will be disabled with the blowing of fuse 7, while fuses 15 and 16 of the column spare decoder of FIG. 2 are programmed by fusing so that the spare decoder may be enabled with the input of column address signals to the normal decoder. On the other hand, the use of the normal decoder means blowing of fuse 17 in the spare decoder.
FIG. 3 is a wave form diagram illustrative of selecting a spare column line in connection with the use of the spare decoder of FIG. 2.
In DRAM devices, when RAS (Row address strobe) is rendered to a logic low state (ground level), row address signals are transmitted. In the low state of RAS, when CAS is rendered low in the static column mode, column address signals are transmitted to the column spare decoder. In this case, whenever the transition of column address signals arises, such detected transition clock is a reset clock RST shown in FIG. 2. The reset clock RST is coupled to a gate of N channel MOS transistor 12 of FIG. 2.
To produce such a clock, the column address transition detection circuit is inevitably required to be arranged on the same chip. This necessitates increased chip size.
Another problem is of the power consumption because, whenever the reset clock RST is applied to the gate of the transistor 12, the transistor 12 and at least one of transistors 10A (or 10B) through 11A (or 11B) conduct.